Invention Grant
US08281191B2 Fully-buffered dual in-line memory module with fault correction
有权
具有故障校正功能的全缓冲双列直插式内存模块
- Patent Title: Fully-buffered dual in-line memory module with fault correction
- Patent Title (中): 具有故障校正功能的全缓冲双列直插式内存模块
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Application No.: US12903606Application Date: 2010-10-13
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Publication No.: US08281191B2Publication Date: 2012-10-02
- Inventor: Sehat Sutardja , Saeed Azimi
- Applicant: Sehat Sutardja , Saeed Azimi
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: G11C29/00
- IPC: G11C29/00
Abstract:
A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal.
Public/Granted literature
- US20110029752A1 FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION Public/Granted day:2011-02-03
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