Invention Grant
US08281214B2 Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
用于读通道的可编程准循环低密度奇偶校验(QC LDPC)编码器

Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
Abstract:
The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
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