An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.