Invention Grant
US08281221B2 Operation method of MRAM including correcting data for single-bit error and multi-bit error
有权
MRAM的操作方法包括纠正单位错误和多位错误的数据
- Patent Title: Operation method of MRAM including correcting data for single-bit error and multi-bit error
- Patent Title (中): MRAM的操作方法包括纠正单位错误和多位错误的数据
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Application No.: US12083373Application Date: 2006-10-17
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Publication No.: US08281221B2Publication Date: 2012-10-02
- Inventor: Noboru Sakimura , Takeshi Honda , Tadahiko Sugibayashi
- Applicant: Noboru Sakimura , Takeshi Honda , Tadahiko Sugibayashi
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2005-303351 20051018
- International Application: PCT/JP2006/320610 WO 20061017
- International Announcement: WO2007/046350 WO 20070426
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.
Public/Granted literature
- US20090125787A1 Operation Method of Mram Public/Granted day:2009-05-14
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