Invention Grant
US08281271B1 Method and apparatus for performing lutmask based delay modeling
有权
用于执行基于掩码的延迟建模的方法和装置
- Patent Title: Method and apparatus for performing lutmask based delay modeling
- Patent Title (中): 用于执行基于掩码的延迟建模的方法和装置
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Application No.: US12287828Application Date: 2008-10-14
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Publication No.: US08281271B1Publication Date: 2012-10-02
- Inventor: Jungmoo Oh , Lyndon Francis Carvalho , Chris Wysocki
- Applicant: Jungmoo Oh , Lyndon Francis Carvalho , Chris Wysocki
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agent L. Cho
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified.
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