Invention Grant
US08281272B1 System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
有权
从具有分层参数的IC设计中的原理图组件生成可重复使用的布局组件的系统和方法
- Patent Title: System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
- Patent Title (中): 从具有分层参数的IC设计中的原理图组件生成可重复使用的布局组件的系统和方法
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Application No.: US13270056Application Date: 2011-10-10
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Publication No.: US08281272B1Publication Date: 2012-10-02
- Inventor: Arnold Ginetti
- Applicant: Arnold Ginetti
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50 ; G06F15/04
Abstract:
A method is provided to produce an integrated circuit layout design comprising: providing in non-transitory storage a pPar parent cell that includes one or more pPar instances and that specifies one or more corresponding input parameter values; producing a graphical representation on a computer display screen of a first schematic design that includes a pPar parent instance; instantiating in non-transitory storage a parameterized cell supermaster that corresponds to the pPar parent cell; determining whether a core layout cell is stored in non-transitory storage that corresponds to the parameterized cell supermaster and the one or more corresponding input parameter values; in response to determining that such a core layout cell is stored, filling a first parameterized cell submaster with an instance of the stored core layout cell; in response to determining that such a core layout cell is not stored, using program code associated with the parameterized cell supermaster to generate a core layout cell; and storing the generated core layout cell in non-transitory storage.
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