Invention Grant
- Patent Title: Reducing leakage power in integrated circuit designs
- Patent Title (中): 降低集成电路设计中的漏电功率
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Application No.: US13220603Application Date: 2011-08-29
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Publication No.: US08281275B2Publication Date: 2012-10-02
- Inventor: Sridhar Tirumala
- Applicant: Sridhar Tirumala
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values.
Public/Granted literature
- US20120131531A1 Reducing Leakage Power in Integrated Circuit Designs Public/Granted day:2012-05-24
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