Invention Grant
US08283209B2 Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
有权
半导体器件和用导电凸块互连的具有内部已知的良好裸芯片的PiP的形成方法
- Patent Title: Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
- Patent Title (中): 半导体器件和用导电凸块互连的具有内部已知的良好裸芯片的PiP的形成方法
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Application No.: US12635631Application Date: 2009-12-10
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Publication No.: US08283209B2Publication Date: 2012-10-09
- Inventor: Zigmund R. Camacho , Frederick R. Dahilig , Lionel Chien Hui Tay
- Applicant: Zigmund R. Camacho , Frederick R. Dahilig , Lionel Chien Hui Tay
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
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