Invention Grant
US08283664B2 Disguising test pads in a semiconductor package 有权
伪装半导体封装中的测试焊盘

Disguising test pads in a semiconductor package
Abstract:
A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.
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