Invention Grant
US08283726B2 System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors
有权
用于制造核心晶体管的工艺制造的具有多晶硅区域的I / O ESD保护的系统和方法
- Patent Title: System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors
- Patent Title (中): 用于制造核心晶体管的工艺制造的具有多晶硅区域的I / O ESD保护的系统和方法
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Application No.: US12623363Application Date: 2009-11-20
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Publication No.: US08283726B2Publication Date: 2012-10-09
- Inventor: Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
- Applicant: Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN200610027589 20060612
- Main IPC: H01L23/62
- IPC: H01L23/62

Abstract:
A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers.
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