Invention Grant
- Patent Title: High voltage tolerant bus holder circuit and method of operating the circuit
- Patent Title (中): 高耐压母线电路和操作电路的方法
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Application No.: US13152764Application Date: 2011-06-03
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Publication No.: US08283947B1Publication Date: 2012-10-09
- Inventor: Jayarama Ubaradka , Dharmaray M. Nedalgi
- Applicant: Jayarama Ubaradka , Dharmaray M. Nedalgi
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H03K19/0175
- IPC: H03K19/0175

Abstract:
A high voltage tolerant bus holder circuit and method of operating the bus holder circuit utilizes first and second control transistors connected in parallel between a control terminal of a pull-up transistor and a bus. The first control transistor is used to turn on the pull-up transistor during a pull-up mode of operation. The second control transistor is used to turn off the pull-down transistor when a voltage on the bus exceeds a threshold.
Information query
IPC分类: