Invention Grant
- Patent Title: Method of manufacturing a semiconductor package and semiconductor package having an electrode pad with a small pitch
- Patent Title (中): 制造半导体封装的方法和具有小间距的电极焊盘的半导体封装
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Application No.: US12749117Application Date: 2010-03-29
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Publication No.: US08288875B2Publication Date: 2012-10-16
- Inventor: Noriyoshi Shimizu , Akio Rokugawa
- Applicant: Noriyoshi Shimizu , Akio Rokugawa
- Applicant Address: JP Nagano-shi, Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi, Nagano
- Agency: Drinker Biddle & Reath LLP
- Priority: JPP.2009-081922 20090330
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/04
Abstract:
A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed.
Public/Granted literature
- US20100244280A1 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE Public/Granted day:2010-09-30
Information query
IPC分类:
