Invention Grant
US08291126B2 Variable read latency on a serial memory bus 有权
串行存储器总线上的可变读延迟

Variable read latency on a serial memory bus
Abstract:
One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
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