Invention Grant
- Patent Title: Variable read latency on a serial memory bus
- Patent Title (中): 串行存储器总线上的可变读延迟
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Application No.: US12729905Application Date: 2010-03-23
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Publication No.: US08291126B2Publication Date: 2012-10-16
- Inventor: Clifford Alan Zitlaw
- Applicant: Clifford Alan Zitlaw
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Frommer, Lawrence & Haug LLP
- Agent Matthew M. Gaffney
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F13/00

Abstract:
One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
Public/Granted literature
- US20110238866A1 VARIABLE READ LATENCY ON A SERIAL MEMORY BUS Public/Granted day:2011-09-29
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