Invention Grant
US08291223B2 Arithmetic circuit for montgomery multiplication and encryption circuit
有权
用于montgomery乘法和加密电路的算术电路
- Patent Title: Arithmetic circuit for montgomery multiplication and encryption circuit
- Patent Title (中): 用于montgomery乘法和加密电路的算术电路
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Application No.: US12686185Application Date: 2010-01-12
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Publication No.: US08291223B2Publication Date: 2012-10-16
- Inventor: Shigeo Ohyama
- Applicant: Shigeo Ohyama
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JP2009-006262 20090115
- Main IPC: G06F21/00
- IPC: G06F21/00

Abstract:
An arithmetic circuit capable of Montgomery multiplication using only a one-port RAM is disclosed. In a first read process, b[i] is read from a memory M2 of a sync one-port RAM for storing a[s−1: 0] and b[s−1: 0] and stored in a register R1. In a second read process, a[j] is read from the memory M2, t[j] from a memory M1 of a sync one-port RAM for storing t[s−1: 0], b[i] from the register R1, and a value RC from a register R2, and input to a sum-of-products calculation circuit for calculating t[j]+a[j]*b[i]+RC. In a write process, the calculation result data FH is written in the register R2, and the calculation result data FL in the memory M1 as t[j]. A first subloop process for repeating the second read process, the sum-of-products calculation process and the write process is executed after the first read process.
Public/Granted literature
- US20100183145A1 ARITHMETIC CIRCUIT FOR MONTGOMERY MULTIPLICATION AND ENCRYPTION CIRCUIT Public/Granted day:2010-07-22
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