Invention Grant
- Patent Title: Vertically stacked fin transistors and methods of fabricating and operating the same
- Patent Title (中): 垂直堆叠鳍式晶体管及其制造和操作方法
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Application No.: US12950761Application Date: 2010-11-19
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Publication No.: US08294511B2Publication Date: 2012-10-23
- Inventor: Werner Juengling
- Applicant: Werner Juengling
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder
- Main IPC: H01L25/00
- IPC: H01L25/00

Abstract:
A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.
Public/Granted literature
- US20120126883A1 VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME Public/Granted day:2012-05-24
Information query
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