Invention Grant
US08295121B2 Clock buffer and a semiconductor memory apparatus using the same 有权
时钟缓冲器和使用其的半导体存储装置

Clock buffer and a semiconductor memory apparatus using the same
Abstract:
A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.
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