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US08296256B2 SAT-based synthesis of a clock gating function 有权
基于SAT的时钟门控功能的综合

SAT-based synthesis of a clock gating function
Abstract:
Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.
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