Invention Grant
US08296611B2 Test circuit for input/output array and method and storage device thereof
有权
输入/输出阵列的测试电路及其方法和存储装置
- Patent Title: Test circuit for input/output array and method and storage device thereof
- Patent Title (中): 输入/输出阵列的测试电路及其方法和存储装置
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Application No.: US12748455Application Date: 2010-03-29
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Publication No.: US08296611B2Publication Date: 2012-10-23
- Inventor: Min-Chung Chou
- Applicant: Min-Chung Chou
- Applicant Address: TW Hsinchu
- Assignee: Elite Semiconductor Memory Technology Inc.
- Current Assignee: Elite Semiconductor Memory Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H03M13/00

Abstract:
The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.
Public/Granted literature
- US20110239046A1 TEST CIRCUIT FOR INPUT/OUTPUT ARRAY AND METHOD AND STORAGE DEVICE THEREOF Public/Granted day:2011-09-29
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