Invention Grant
- Patent Title: Method and apparatus for performing static analysis optimization in a design verification system
- Patent Title (中): 在设计验证系统中执行静态分析优化的方法和装置
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Application No.: US11725288Application Date: 2007-03-19
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Publication No.: US08296697B2Publication Date: 2012-10-23
- Inventor: Amit Gal , Shlomi Uziel , Amos Noy
- Applicant: Amit Gal , Shlomi Uziel , Amos Noy
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Brian J. Colandreo, Esq.; Mark H. Whittenberger, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
Public/Granted literature
- US20080235640A1 Method and apparatus for performing static analysis optimization in a design verification system Public/Granted day:2008-09-25
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