Invention Grant
- Patent Title: Timing adjustment circuit, timing adjustment method, and correction value computing method
- Patent Title (中): 定时调整电路,时序调整方法和校正值计算方法
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Application No.: US12784029Application Date: 2010-05-20
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Publication No.: US08300483B2Publication Date: 2012-10-30
- Inventor: Hiroyuki Sano
- Applicant: Hiroyuki Sano
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2009-123459 20090521
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A timing adjustment circuit includes a determination unit for outputting delay information corresponding to a period of a first input signal, a storing unit for storing a plurality of correction values based on a circuit included in the determination unit, a correction unit for correcting the delay information based on a correction value selected from the plurality of the correction values, based on the delay information, and a first delay line for delaying a second input signal corresponding to the first input signal, based on the delay information corrected by the correction unit.
Public/Granted literature
- US20100296351A1 TIMING ADJUSTMENT CIRCUIT, TIMING ADJUSTMENT METHOD, AND CORRECTION VALUE COMPUTING METHOD Public/Granted day:2010-11-25
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