Invention Grant
US08301844B2 Consistency evaluation of program execution across at least one memory barrier
有权
至少一个记忆障碍的程序执行的一致性评估
- Patent Title: Consistency evaluation of program execution across at least one memory barrier
- Patent Title (中): 至少一个记忆障碍的程序执行的一致性评估
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Application No.: US10756534Application Date: 2004-01-13
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Publication No.: US08301844B2Publication Date: 2012-10-30
- Inventor: Simon C. Steely, Jr. , Gregory Edward Tierney
- Applicant: Simon C. Steely, Jr. , Gregory Edward Tierney
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G06F13/38
- IPC: G06F13/38

Abstract:
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.
Public/Granted literature
- US20050154832A1 Consistency evaluation of program execution across at least one memory barrier Public/Granted day:2005-07-14
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