Invention Grant
- Patent Title: Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization
- Patent Title (中): 在分层电路布局优化中获得可行整数解的方法
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Application No.: US12712880Application Date: 2010-02-25
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Publication No.: US08302062B2Publication Date: 2012-10-30
- Inventor: Michael S. Gray , Xiaoping Tang , Xin Yuan
- Applicant: Michael S. Gray , Xiaoping Tang , Xin Yuan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Richard M. Kotulak
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
Public/Granted literature
- US20100153892A1 METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION Public/Granted day:2010-06-17
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