Invention Grant
US08304322B2 Methods of filling isolation trenches for semiconductor devices and resulting structures
有权
填充用于半导体器件和所得结构的隔离沟槽的方法
- Patent Title: Methods of filling isolation trenches for semiconductor devices and resulting structures
- Patent Title (中): 填充用于半导体器件和所得结构的隔离沟槽的方法
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Application No.: US11405629Application Date: 2006-04-18
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Publication No.: US08304322B2Publication Date: 2012-11-06
- Inventor: Paul J. Rudeck , Sukesh Sandhu
- Applicant: Paul J. Rudeck , Sukesh Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: H01L21/76
- IPC: H01L21/76
Abstract:
The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique.
Public/Granted literature
- US20070243692A1 Methods of filling isolation trenches for semiconductor devices and resulting structures Public/Granted day:2007-10-18
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