Invention Grant
- Patent Title: Semiconductor package and manufacturing method of the same
- Patent Title (中): 半导体封装及其制造方法相同
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Application No.: US12644390Application Date: 2009-12-22
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Publication No.: US08304862B2Publication Date: 2012-11-06
- Inventor: Yuichi Taguchi , Mitsutoshi Higashi , Akinori Shiraishi , Hideaki Sakaguchi , Masahiro Sunohara
- Applicant: Yuichi Taguchi , Mitsutoshi Higashi , Akinori Shiraishi , Hideaki Sakaguchi , Masahiro Sunohara
- Applicant Address: JP Nagano-shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2008-328257 20081224
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/60 ; H01L23/48
Abstract:
A semiconductor package includes: a wiring board; and a semiconductor device which is formed on the wiring board; wherein the semiconductor device includes: a semiconductor chip; and a penetration electrode, one end of which is fixed on one plane of the semiconductor chip, and the other end of which penetrates the semiconductor chip and is fixed on the other plane of the semiconductor chip, the penetration electrode penetrating the semiconductor chip in such a manner that the penetration electrode is not contacted to a wall plane of the semiconductor chip by a space portion formed in the semiconductor chip; and the wiring board and the semiconductor device are electrically connected via the penetration electrode.
Public/Granted literature
- US20100155928A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME Public/Granted day:2010-06-24
Information query
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