Invention Grant
- Patent Title: High-performance memory interface circuit architecture
- Patent Title (中): 高性能存储器接口电路架构
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Application No.: US13168499Application Date: 2011-06-24
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Publication No.: US08305121B1Publication Date: 2012-11-06
- Inventor: Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
- Applicant: Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ward & Zinna, LLC
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
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