Invention Grant
- Patent Title: Flop type selection for very large scale integrated circuits
- Patent Title (中): 非常大型集成电路的Flop型选择
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Application No.: US13005835Application Date: 2011-01-13
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Publication No.: US08305126B2Publication Date: 2012-11-06
- Inventor: Alan P. Smith , Robert P. Masleid , Georgios Konstadinidis
- Applicant: Alan P. Smith , Robert P. Masleid , Georgios Konstadinidis
- Applicant Address: US CA Redwood City
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood City
- Agency: Meyertons Hood Kivlin Kowert & Goetzel
- Agent Erik A. Heter
- Main IPC: H03K3/289
- IPC: H03K3/289 ; G01R35/00

Abstract:
A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.
Public/Granted literature
- US20120182055A1 FLOP TYPE SELECTION FOR VERY LARGE SCALE INTEGRATED CIRCUITS Public/Granted day:2012-07-19
Information query
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