Disclosed is an improved electrostatic discharge protection device that can effectively cope with electrostatic stress of a microchip operating at high voltage. The ESD protection device includes at least one gate coupled NMOS (GCNMOS) having a gate connected to a drain via a capacitor disposed between the gate and the drain and connected to a source and a well to pick-up via a resistor, and devices for low or medium voltage operation of 6V or less connected in series to the gate coupled NMOS (GCNMOS).