Invention Grant
US08305791B2 Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof
有权
存储电路具有与所有位线电隔离的公共源/漏区的存储单元，其系统及其制造方法
- Patent Title: Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof
- Patent Title (中): 存储电路具有与所有位线电隔离的公共源/漏区的存储单元，其系统及其制造方法
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Application No.: US12784133Application Date: 2010-05-20
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Publication No.: US08305791B2Publication Date: 2012-11-06
- Inventor: Ching-Wei Wu , Cheng Hung Lee , Li-Chen Chen , Weiyang Jiang
- Applicant: Ching-Wei Wu , Cheng Hung Lee , Li-Chen Chen , Weiyang Jiang
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: G11C17/00
- IPC: G11C17/00
Abstract:
A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.
Public/Granted literature
- US20110019460A1 MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF Public/Granted day:2011-01-27
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