Invention Grant
US08305793B2 Integrated circuit with an array of resistance changing memory cells
有权
具有电阻变化存储单元阵列的集成电路
- Patent Title: Integrated circuit with an array of resistance changing memory cells
- Patent Title (中): 具有电阻变化存储单元阵列的集成电路
-
Application No.: US12122091Application Date: 2008-05-16
-
Publication No.: US08305793B2Publication Date: 2012-11-06
- Inventor: Petra Majewski , Jan Boris Philipp
- Applicant: Petra Majewski , Jan Boris Philipp
- Applicant Address: DE Munich
- Assignee: Qimonda AG
- Current Assignee: Qimonda AG
- Current Assignee Address: DE Munich
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
An integrated circuit includes an array of resistance changing memory cells, and a circuit configured to apply an initialization signal to a first one of the memory cells that is in a virgin resistance state. The initialization signal is configured to modify the first memory cell without switching an operation state of the first memory cell.
Public/Granted literature
- US20090285007A1 INTEGRATED CIRCUIT WITH AN ARRAY OF RESISTANCE CHANGING MEMORY CELLS Public/Granted day:2009-11-19
Information query
