Invention Grant
US08305829B2 Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
有权
用于控制存储器阵列的内部电压的存储器电源门控电路，用于控制存储器阵列的系统和方法
- Patent Title: Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
- Patent Title (中): 用于控制存储器阵列的内部电压的存储器电源门控电路，用于控制存储器阵列的系统和方法
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Application No.: US12707788Application Date: 2010-02-18
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Publication No.: US08305829B2Publication Date: 2012-11-06
- Inventor: Wei Min Chan , Jack Liu , Shao-Yu Chou
- Applicant: Wei Min Chan , Jack Liu , Shao-Yu Chou
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.
Public/Granted literature
- US20100214863A1 MEMORY POWER GATING CIRCUIT AND METHODS Public/Granted day:2010-08-26
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