A clock regeneration circuit according to the present invention that generates a clock signal that is synchronized to an input signal, includes: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.