Invention Grant
- Patent Title: Fine-grained gear-shifting of a digital phase-locked loop (PLL)
- Patent Title (中): 数字锁相环(PLL)的细粒度换档
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Application No.: US10464982Application Date: 2003-06-19
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Publication No.: US08306176B2Publication Date: 2012-11-06
- Inventor: Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
- Applicant: Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.
Public/Granted literature
- US20030235262A1 Fine-grained gear-shifting of a digital phase-locked loop (PLL) Public/Granted day:2003-12-25
Information query
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