Invention Grant
- Patent Title: Method for modeling an HDL design using symbolic simulation
- Patent Title (中): 使用符号模拟建模HDL设计的方法
-
Application No.: US11556050Application Date: 2006-11-02
-
Publication No.: US08306802B2Publication Date: 2012-11-06
- Inventor: Yunshan Zhu , James Herbert Kukula , Robert F. Damiano , Joseph T. Buck
- Applicant: Yunshan Zhu , James Herbert Kukula , Robert F. Damiano , Joseph T. Buck
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with identifying and capturing the combinational logic expression of the simulation output and the next state functions of the simulation.
Public/Granted literature
- US20080126066A1 Method for Modeling an HDL Design Using Symbolic Simulation Public/Granted day:2008-05-29
Information query