Invention Grant
- Patent Title: System, an apparatus and a method for performing chip-level electrostatic discharge simulations
- Patent Title (中): 用于执行芯片级静电放电模拟的系统,装置和方法
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Application No.: US12434573Application Date: 2009-05-01
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Publication No.: US08306804B2Publication Date: 2012-11-06
- Inventor: Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
- Applicant: Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.
Public/Granted literature
- US20100169064A1 SYSTEM, AN APPARATUS AND A METHOD FOR PERFORMING CHIP-LEVEL ELECTROSTATIC DISCHARGE SIMULATIONS Public/Granted day:2010-07-01
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