A multi-core processor which includes a plurality of processor dies. The multi-core processor has a first processor core which processes a first task and a second processor core which processes a second task. The first processor core and the second processor core are formed on each of the plurality of processor dies. When the first processor core makes a request for the second task processing in processing the first task, information on the second task is stored in a memory area used by the first processor core and interrupt notification is made to each of the second processor cores provided respectively on the plurality of processor dies. Each of the second processor cores having received the interrupt notification accesses the memory area used by the first processor core provided on the same processor die as the processor die on which the second processor core is provided.