Invention Grant
US08307260B2 Memory apparatus and method using erasure error correction to reduce power consumption
有权
使用擦除误差校正的存储装置和方法来降低功耗
- Patent Title: Memory apparatus and method using erasure error correction to reduce power consumption
- Patent Title (中): 使用擦除误差校正的存储装置和方法来降低功耗
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Application No.: US13365064Application Date: 2012-02-02
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Publication No.: US08307260B2Publication Date: 2012-11-06
- Inventor: Yutaka Ito , Adrian J. Drexler
- Applicant: Yutaka Ito , Adrian J. Drexler
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C29/00
- IPC: G11C29/00
Abstract:
Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.
Public/Granted literature
- US20120131419A1 MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION Public/Granted day:2012-05-24
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