Invention Grant
US08307269B2 Scalable folded decoder architecture for low density parity check codes
有权
用于低密度奇偶校验码的可扩展折叠解码器架构
- Patent Title: Scalable folded decoder architecture for low density parity check codes
- Patent Title (中): 用于低密度奇偶校验码的可扩展折叠解码器架构
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Application No.: US12631455Application Date: 2009-12-04
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Publication No.: US08307269B2Publication Date: 2012-11-06
- Inventor: Yuming Zhu , Manish Goel
- Applicant: Yuming Zhu , Manish Goel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.
Public/Granted literature
- US20100115386A1 Scalable Folded Decoder Architecture for Low Density Parity Check Codes Public/Granted day:2010-05-06
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