Invention Grant
- Patent Title: Integrated circuit reliability
- Patent Title (中): 集成电路可靠性的改进或与之有关
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Application No.: US12599152Application Date: 2007-05-15
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Publication No.: US08307319B2Publication Date: 2012-11-06
- Inventor: Hisao Kawasaki , David Ney
- Applicant: Hisao Kawasaki , David Ney
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- International Application: PCT/IB2007/052715 WO 20070515
- International Announcement: WO2008/139277 WO 20081120
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intrinsic parameter at the first defined value.
Public/Granted literature
- US20100301487A1 IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY Public/Granted day:2010-12-02
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