Invention Grant
US08307320B2 Method of placing delay units of pulse delay circuit on programmable logic device
有权
在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法
- Patent Title: Method of placing delay units of pulse delay circuit on programmable logic device
- Patent Title (中): 在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法
-
Application No.: US12661156Application Date: 2010-03-11
-
Publication No.: US08307320B2Publication Date: 2012-11-06
- Inventor: Tomohito Terazawa , Shigenori Yamauchi , Takamoto Watanabe
- Applicant: Tomohito Terazawa , Shigenori Yamauchi , Takamoto Watanabe
- Applicant Address: JP Kariya
- Assignee: Denso Corporation
- Current Assignee: Denso Corporation
- Current Assignee Address: JP Kariya
- Agency: Harness, Dickey & Pierce, PLC
- Priority: JP2009-068509 20090319
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03H11/26

Abstract:
A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
Public/Granted literature
- US20100237923A1 Method of placing delay units of pulse delay circuit on programmable logic device Public/Granted day:2010-09-23
Information query