Invention Grant
- Patent Title: Wafer and method of manufacturing semiconductor device
- Patent Title (中): 晶圆和半导体器件的制造方法
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Application No.: US12901187Application Date: 2010-10-08
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Publication No.: US08310032B2Publication Date: 2012-11-13
- Inventor: Yoshitsugu Kawashima
- Applicant: Yoshitsugu Kawashima
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2009-235173 20091009
- Main IPC: H01L23/544
- IPC: H01L23/544

Abstract:
In a wafer, a first chip region and a second chip region are separated from each other by a dicing region. The dicing region includes: a first center region; a first intermediate region located on the first chip region's side of the first center region; a second intermediate region located on the second chip region's side of the first center region; a first outer region located on the first chip region's side of the first intermediate region; and a second outer region located on the second chip region's side of the second intermediate region. Surfaces of the first and second intermediate regions are respectively covered by bank-shaped resin films extending in a longitudinal direction of the dicing region. Respective surfaces of the first center region, the first outer region and the second outer region are not covered by resin films.
Public/Granted literature
- US20110084364A1 WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2011-04-14
Information query
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