Invention Grant
- Patent Title: Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof
- Patent Title (中): 具有高击穿电压和低寄生电感的半导体器件封装及其制造方法
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Application No.: US12962761Application Date: 2010-12-08
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Publication No.: US08310040B2Publication Date: 2012-11-13
- Inventor: Richard Alfred Beaupre , Paul Alan McConnelee , Arun Virupaksha Gowda , Thomas Bert Gorczyca
- Applicant: Richard Alfred Beaupre , Paul Alan McConnelee , Arun Virupaksha Gowda , Thomas Bert Gorczyca
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Agent Jean K. Testa
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
Public/Granted literature
- US20120146234A1 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF Public/Granted day:2012-06-14
Information query
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