Invention Grant
- Patent Title: Semiconductor device manufacturing method and target substrate processing system
- Patent Title (中): 半导体器件制造方法和目标衬底处理系统
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Application No.: US13178291Application Date: 2011-07-07
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Publication No.: US08310054B2Publication Date: 2012-11-13
- Inventor: Hidenori Miyoshi , Kazuichi Hayashi
- Applicant: Hidenori Miyoshi , Kazuichi Hayashi
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-207909 20070809
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
A semiconductor device manufacturing method includes removing copper deposits, by use of an organic acid gas and an oxidizing gas, from a surface of a second interlayer insulation film having a groove formed therein and reaching a copper-containing electric connector member. The second interlayer insulation film is disposed on a first interlayer insulation film provided with the electric connector member. The method then includes reducing a surface of the electric connector member exposed at a bottom of the groove of the second interlayer insulation film; forming a barrier layer on the second interlayer insulation film; and forming a copper-containing conductive film to fill the groove of the second interlayer insulation film.
Public/Granted literature
- US20110265950A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND TARGET SUBSTRATE PROCESSING SYSTEM Public/Granted day:2011-11-03
Information query
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