According to the embodiments, a semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, and a row selector that multiply-selects the word lines, wherein the semiconductor storage device satisfies Ncell/NWL≦(4×Cbl×VDD)/(Icell×Tcyc), where Ncell is number of memory cells connected to each of the bit lines, NWL is a unit of number of word lines multiply-selected by the row selector, Cbl is a value obtained by dividing a capacitance of the bit line by Ncell, VDD is a power supply voltage, Tcyc is an operating frequency of each of the memory cells, and Icell is a target value of current read out via each of the bit lines.