According to one embodiment, electrical test results of a semiconductor memory arrayed in a logical address order are stored in a first memory secured in a main memory, a plurality of second memory areas in each of which loading and storing of each data in a unit size is performed is secured in the main memory, FBMs in which pass/fail information is arrayed in a physical address order are generated based on different parts of the electrical test results stored in the first memory area, respectively, the FBMs generated from the different parts of the electrical test results are stored in the second memory areas, respectively, and the FBMs stored in the second memory areas, respectively, are output.