Invention Grant
- Patent Title: Semiconductor devices having polysilicon gate layer patterns and methods of manufacturing the same
- Patent Title (中): 具有多晶硅栅极层图案的半导体器件及其制造方法
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Application No.: US12805400Application Date: 2010-07-29
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Publication No.: US08319260B2Publication Date: 2012-11-27
- Inventor: Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
- Applicant: Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2009-0093902 20091001
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.
Public/Granted literature
- US20110079857A1 Semiconductor devices and methods of manufacturing the same Public/Granted day:2011-04-07
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