Invention Grant
US08319295B2 Use of F-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies
有权
使用基于F的栅极蚀刻来钝化高k /金属栅极叠层,用于深亚微米晶体管技术
- Patent Title: Use of F-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies
- Patent Title (中): 使用基于F的栅极蚀刻来钝化高k /金属栅极叠层,用于深亚微米晶体管技术
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Application No.: US11971845Application Date: 2008-01-09
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Publication No.: US08319295B2Publication Date: 2012-11-27
- Inventor: Nadine Collaert , Paul Zimmerman , Marc Demand , Werner Boullart , Adelina K. Shickova
- Applicant: Nadine Collaert , Paul Zimmerman , Marc Demand , Werner Boullart , Adelina K. Shickova
- Applicant Address: BE Leuven BE Leuven
- Assignee: IMEC,Katholieke Universiteit Leuven, K.U. Leuven R&D
- Current Assignee: IMEC,Katholieke Universiteit Leuven, K.U. Leuven R&D
- Current Assignee Address: BE Leuven BE Leuven
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/302

Abstract:
A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.
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