Invention Grant
- Patent Title: System for detecting a reset condition in an electronic circuit
- Patent Title (中): 用于检测电子电路中的复位状态的系统
-
Application No.: US13533661Application Date: 2012-06-26
-
Publication No.: US08319533B2Publication Date: 2012-11-27
- Inventor: Jay Scott Fuller
- Applicant: Jay Scott Fuller
- Applicant Address: CA Mississauga
- Assignee: Certicom Corp.
- Current Assignee: Certicom Corp.
- Current Assignee Address: CA Mississauga
- Agency: Novak Druce + Quigg LLP
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.
Public/Granted literature
- US20120268174A1 SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT Public/Granted day:2012-10-25
Information query