Invention Grant
- Patent Title: Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers
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Application No.: US13137733Application Date: 2011-09-08
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Publication No.: US08324043B2Publication Date: 2012-12-04
- Inventor: Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
- Applicant: Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2008-0115801 20081120
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.
Public/Granted literature
- US20120003799A1 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers Public/Granted day:2012-01-05
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