Invention Grant
- Patent Title: Methods and apparatus for disabling a memory-array portion
- Patent Title (中): 用于禁用存储器阵列部分的方法和装置
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Application No.: US12639599Application Date: 2009-12-16
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Publication No.: US08325557B2Publication Date: 2012-12-04
- Inventor: Daniel R. Shepard
- Applicant: Daniel R. Shepard
- Applicant Address: US MA North Billerica
- Assignee: Contour Semiconductor, Inc.
- Current Assignee: Contour Semiconductor, Inc.
- Current Assignee Address: US MA North Billerica
- Agency: Bingham McCutchen LLP
- Main IPC: G11C8/00
- IPC: G11C8/00
Abstract:
A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection.
Public/Granted literature
- US20100157646A1 METHODS AND APPARATUS FOR DISABLING A MEMORY-ARRAY PORTION Public/Granted day:2010-06-24
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