Invention Grant
US08327112B2 Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
有权
处理系统实现可变页大小的存储器组织使用多页每个条目翻译后备缓冲区
- Patent Title: Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
- Patent Title (中): 处理系统实现可变页大小的存储器组织使用多页每个条目翻译后备缓冲区
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Application No.: US13018492Application Date: 2011-02-01
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Publication No.: US08327112B2Publication Date: 2012-12-04
- Inventor: Brian Stecher
- Applicant: Brian Stecher
- Applicant Address: CA Ottawa
- Assignee: QNX Software Systems Limited
- Current Assignee: QNX Software Systems Limited
- Current Assignee Address: CA Ottawa
- Agency: Brinks Hofer Gilson & Lione
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a corresponding physical address page. The processing system also includes a translation lookaside buffer adapted to cache page table information. The processing system also includes memory management software responsive to changes in the page table to consolidate a run of contiguous page table entries into one or more page table entries having a larger memory page size, Y. The memory management software further determines whether the run of contiguous page table entries may be cached in an entry of the translation lookaside buffer that caches multiple page table entries, X, in a single translation lookaside buffer entry.
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